The invention pertains to measurement of linewidths in semiconductor devices, and particularly to techniques that improve linewidth measurements made by electrical linewidth measurement (ELM) techniques.
Integrated circuits (ICs) are manufactured by forming discrete semiconductor devices such as MOSFETS and bipolar junction transistors on the surface of a silicon wafer, and then creating conductive lines that connect the devices to create circuits. A variety of materials may be used to form the lines, including metals, doped polysilicon, and silicon/metal alloys, also known as silicides. Presently, doped polysilicon (referred to hereinafter as polysilicon) is gaff the preferred line material.
Integrated circuit elements and connecting lines are typically formed by projection lithography processes. In general, projection lithography is a process whereby a pattern to be formed on a substrate is projected onto a photosensitive coating (hereinafter photoresist) applied to the substrate, thereby exposing the photoresist to the pattern. Subsequent development processes remove either the exposed portion of the photoresist or the unexposed portion, leaving behind a photoresist structure (hereinafter mask) in the shape of either the projected pattern or a negative image of the projected pattern. The photoresist mask is then utilized as a barrier in further processing steps. For example, the photoresist mask may protect portions of the substrate from being etched away in an etching process, or may protect portions of the substrate from being implanted with dopant during an implantation process.
The size and location of structures formed through projection lithography techniques are affected by many variables. As a result, it is necessary to test structures produced by lithography to determine whether their actual dimensions and positions coincide with the intended dimensions and positions.
One feature for which dimensional testing is critical is the physical linewidth of polysilicon lines. As the critical dimensions of semiconductor devices become smaller, linewidths become correspondingly small, and thus are more easily subjected to error. Present MOSFET technology providing gate lengths of 0.13 xcexcm utilizes corresponding physical linewidths of between 50 nm and 80 nm.
The most accurate tool for determining physical linewidth is the scanning electron microscope (SEM). However, the accuracy provided by the SEM varies depending on the orientation of the SEM. The side walls of a line typically have a rough and sloping profile. If the SEM is used in a vertical orientation to provide a cross-sectional view of the line, the width of the line at each point along its height is measured and one of those points, e.g. the uppermost point, can be chosen as representing the actual physical linewidth. In contrast, if the SEM is used in a top-down orientation to provide a top view, it is difficult to determine where within the slope of the line side walls the measurement is being made. Thus, an SEM measurement made in a top-down orientation will typically indicate that the line is wider than it actually is. In both cases, the SEM method is expensive and time consuming, and therefore is not appropriate for production environments.
Another method for determining physical linewidth is through electrical linewidth measurement (ELM). Unlike the SEM methods, ELM linewidth measurement provides relatively rapid results along with good reliability, and is therefore more desirable for production environments. However, as the name implies, electrical linewidth measurement measures the xe2x80x9celectrical widthxe2x80x9d of the line rather than its physical width. The difference between actual physical linewidth and the electrical linewidth measured by ELM, referred to hereinafter as the offset, is typically in the range of 50 nm-100 nm. For prior generation technology, an offset of 100 nm was not significant in relation to the typical physical linewidth, and therefore ELM was employed for linewidth measurement in prior generation production environments despite the fact that its results did not precisely represent the physical linewidths of the measured lines. However, as next generation linewidths approach and exceed the value of the conventional offset, the ELM offset becomes significant and renders the technique unusable.
The ELM method determines the electrical width of a conducting structure based on sheet resistivity. FIG. 1 shows an example of a linewidth test structure produced for ELM. The structure includes two test cells 10 and 12. The first cell 10 includes a Van der Pauw structure 14 formed of polysilicon, and four polysilicon contact pads 18, 20, 22 and 24 that are connected to the four corners of the Van der Pauw structure 14. The second test cell 12 includes a polysilicon line 16 having a known length L and a linewidth width W that is to be determined by testing. The second test cell 12 further includes four polysilicon contact pads 22, 24, 26 and 28 that are connected to the line 16.
The Van der Pauw structure 14, the polysilicon line 16 and the contact pads are formed at the same time and thus have the same material composition. The first test cell 10 of the test structure is used to determine the sheet resistivity "sgr" of the polysilicon Van der Pauw structure 14 using the well-known Van der Pauw method. The sheet resistivity "sgr" is determined from the resistance RV of the Van der Pauw structure measured using the four contact pads of the first cell, and is given by the relationship "sgr"=RVxcfx80/In2. The linewidth W of the polysilicon line 16 is then determined by applying a constant current to the line 16 and measuring the voltage drop across the known length L of the line using the four contact pads of the second cell to determine the resistance RL of the line. The linewidth is given by the relationship W="sgr"L/RL.
The offset between actual physical linewidth and linewidth measured by ELM is believed to be caused by dopant depletion within the polysilicon line. More particularly, during annealing of the polysilicon line to active implanted dopant, a portion of the dopant near the surfaces of the line is out-diffused, resulting in depletion of dopant within the line and formation of depletion regions near the surfaces of the line. Thus the average sheet resistivity for the line as a whole is greater than the sheet resistivity value used in the electrical linewidth determination, and so the electrical linewidth determined by ELM is different than the physical linewidth.
Proposals for addressing the ELM offset problem have been put forth by Grenville et al. in their article xe2x80x9cElectrical Critical Dimension Metrology for 100-nm Linewidths and Below,xe2x80x9d published in Optical Lithography XIII, Proceedings of SPIE Vol. 4000 (2000) (xe2x80x9cGrenvillexe2x80x9d). Grenville proposes four solutions for reducing out-diffusion of dopant. First, Grenville proposes the use of P-type dopant for providing conductivity in polysilicon, because P-type dopant experiences less out-diffusion during annealing. Second, Grenville proposes lowering the annealing temperature to reduce out-diffusion. Third, Grenville proposes formation of a silicon nitride cap over the polysilicon before annealing to trap dopant within the polysilicon. Fourth, Grenville proposes reducing the thickness of the polysilicon line. Through a combination of these techniques, Grenville has lowered the ELM offset of an experimental polysilicon line from 90 nm to 20 nm. However, Grenville""s techniques entail disadvantages that are undesirable in the production environment. For example, lowering the annealing temperature results in reduced activation of dopant, and consequently results in higher polysilicon resistance, the effects of which become detrimental to the ELM method as linewidth decreases. The additional fabrication steps involved in depositing and subsequently removing a silicon nitride cap add further cost and complexity to the fabrication process.
Consequently, there remains a need for a solution to the ELM offset problem that is easily applied in the production environment without adding significant additional processing steps to the conventional polysilicon line formation process.
Embodiments of the invention address the foregoing shortcomings of the conventional technology by providing a method for forming a test structure for determining polysilicon linewidth by ELM measurement that significantly reduces the ELM offset in comparison to conventional test structures. In accordance with embodiments of the invention, a test structure is formed by patterning a polysilicon line and implanting and activating a P-type dopant. However, prior to implanting the dopant, the polysilicon line is implanted with N2. The N2 treatment significantly reduces out-diffusion of dopant during annealing. Accordingly, less depletion occurs and the linewidth measurement obtained by ELM has a much smaller offset with respect to actual physical linewidth than in conventional technology.
Embodiments of the invention pertain to a method of determining a linewidth of a polysilicon line formed by a lithographic process. A polysilicon layer is formed on a substrate. A line is patterned from said polysilicon layer using said lithographic process and a Van der Pauw structure is patterned from said polysilicon layer. N2 is then implanted into the polysilicon line and the polysilicon Van der Pauw structure to form a depletion barrier. A P-type dopant is the implanted into the polysilicon line and the polysilicon Van der Pauw structure and the dopant is activated. A sheet resistivity of the Van der Pauw structure is determined, and the linewidth of the polysilicon line is then determined by electrical linewidth measurement using the sheet resistivity of the Van der Pauw structure as the sheet resistivity of the polysilicon line. In further embodiments, the dose of N2 may be determined in accordance with an expected linewidth and an acceptable offset.
Further embodiments of the invention pertain to a test structure for electrical linewidth measurement of a linewidth of a polysilicon line formed by a lithographic process. The test structure comprises a polysilicon Van der Pauw structure and a polysilicon line patterned using said lithographic process. The test structure also comprises a plurality of contacts electrically connected to the Van der Pauw structure, and pairs of contacts electrically connected at respective first and second points of the polysilicon line to define a known length L of polysilicon line therebetween. The polysilicon Van der Pauw structure and the polysilicon line comprise a P-type dopant and implanted N2 that serves as a depletion barrier against out-diffusion of the P-type dopant.